Probing on conductive bumps, or balls, during wafer level test to make an electrical connection to the integrated circuit (IC) device is typically accomplished during a single pass or contact between a probe card and the IC device. The conductive ball, or bump, application process is intrinsically unclean. In addition to the natural oxide barriers, there are residual organic materials that remain on the surface of the conductive balls. These contaminants create a thin insulating layer that makes it very difficult to achieve and maintain very low contact resistances between the probe needle and the bump, thus, negatively affects test results and ultimately reducing device yields.
As an example, an integrated circuit device containing an Analog to Digital Converter (ADC) typically requires test verification. The test verification of two key parameters F(full scale)set and Z(zero)set is usually considered critical in such cases. Unfortunately, contact resistance during bump probing is often too high to correctly validate the operation of the ADC for these two parameters.
Further, the magnitude and stability of contact and circuit resistances during wafer level test may be dramatically affected by probe, material, and setup related factors.
Some of the factors affecting resistance include, but are not limited to:                Probe needle composition and physical dimensions;        Probe card design, (e.g. planarity of the probe card can vary between ˜±25.0 um;        Bump height variations which may vary between ±15 um;        Variations due to travel of the probe card ranging between 40 um to 60 um); and        Build-up of adherent contaminants on the probe tip contact surface resulting from multiple touchdowns.        
Consequently, in order to control the contact resistance, keep the contact surface free of contaminants, and to stabilize yield, probe cards are frequently cleaned using an abrasive lapping film. This cleaning process reduces probe or tip length. As a result, probe cards are often prematurely “worn-out” due to excessive abrasive cleaning.
Typically, the probe test flow and ADC IC is to probe peripheral Aluminum pads with Tungsten Rhenium needles during which probe test Fset and Zset are validated. Then the bumps are put on the device. However, most customers require validation of the Fset and Zset parameters following the bump application process. Since the final device is sold to the customer without a package interface, final testing of these parameters at an Assembly Test site is not an option. Furthermore, current probing techniques on bumps prohibits the re-verification of the test, because of the resistive issues described above.
If full testing on the bump connections were possible, the probe step on the Aluminum pads could be eliminated. Elimination of this probe step therefore would at a minimum double throughput on the probe floor for the ADC device.